The semiconductor industry is witnessing an increasing demand for low-output-voltage DC—DC converters with very fast transient response and higher power efficiency for high frequency power conversion applications. When the operation frequency reaches 1 MHz or even higher, the power losses of a synchronous buck DC—DC converter will be dominated by the switching losses. Switching losses in a power MOSFET occur during charging/discharging the drain-gate feedback capacitance. The corresponding gate charge is called Miller Charge. Thus, the reduction of Miller capacitance is one of most important focus to improve DC—DC converter efficiency.
Also, as the cell density and speed of a microprocessor increases, more current is needed to power the microprocessor. This means that the DC—DC converter is required to provide a higher output current. The increase of the output current raises the conduction loss of not only the lower switches but also the upper switches in synchronous DC—DC converter. Therefore, in order to power an advanced microprocessor, the power MOSFETS, which are used as the upper and the lower switches in a DC—DC converter must have both low switching power losses and low conduction power losses. The switching losses can be reduced by lowering on-resistance. Unfortunately, lowering the on-resistance raises the Miller capacitance. For example, in order to reduce the on-resistance of a power MOSFET, the most efficient way is to reduce the device cell pitch and increase the total channel width. Both of these result in an increase of the drain-gate overlay area. As the consequence, the device's Miller capacitance, or Miller charge increases.
Due to gate to drain capacitance's significant impact on device switching speed, a series of improvements for minimizing it's impact have been proposed. These improvements include tailoring of source-drain ion implant angles and gate spacers, in order to obtain sufficient gate overlap of source-drains for maintaining low channel resistance, while still minimizing the associated capacitance values. One such effort to minimize Miller capacitance is a process step that locally increases the gate oxide thickness in the region of gate to drain overlap. However, that process is difficult to control because you need to maintain overlap while growing the thick oxide in the bottom of the trench and etching back. Therefore, what is needed is a method that will achieve low switching power losses and low conductivity power losses.